Recently in the field of radio frequency (RF) communications, there has been an increased demand for digitally encrypted voice and high speed data communications. Since the RF spectrum is inherently limited, one must devise a new system concept and organizational features to accommodate the increased demand. A time division multiple access (TDMA) system is one such system which offers more efficient spectrum utilization and increased capacity.
In its simplest form, a TDMA system is comprised of a transmitting base station, which is capable of time multiplexing messages from at least two users on a single RF channel, and one or more remote receiving stations capable of receiving at least one of the time multiplexed messages. Typically, the receiving station would be a mobile or portable radiotelephone capable of transmitting a TDMA message to the base station on a second RF channel.
In a TDMA system, like most digital communications systems, it is necessary to establish a reference clock in the receiving station that is continuously synchronized with the transmit clock to accurately recover the digital data transmitted between the two points. Continuous bit synchronization, as used herein, means that the frequency and phase of the received clock signal must accurately track that of the transmit clock.
One implementation of a TDMA system uses a time division duplex (TDD) slot structure. The TDD system uses one RF channel to send control and communication information between two points. FIG. 1 is an illustration of a control slot 100 for a particular application. This application requires that symbol synchronization for the control slots 100 be carried out independently for each slot. To aid in the synchronization a 62-bit preamble 101 is provided at the start of each slot 100. A conventional decision-directed clock recovery system would have two problems with this slot structure. First, the 62-bit (31-symbols for quadrature phase shift keying modulation) preamble 101 does not provide sufficient time for symbol timing acquisition. Second, the 62-bit preamble has false-lock points which can cause a decision-directed system to move toward an incorrect sampling phase. Thus, the conventional clock recovery approach for the control slots 100 would be to correlate the detected signal with the known bit pattern.
FIG. 2 is an illustration of a communications slot 200 for a specific application. The communications slot 200 has an extremely short preamble pattern 201 of 6 bits. A correlator-based clock recovery system would not be appropriate for the communication slot 200 because it requires a longer preamble to lock onto the received data signal. As a result, the conventional solution to the clock recovery problem would be to use a correlation-based system for the control slots 100 and a decision-directed clock recovery scheme for the communications slots 200. However, two different system implementations would result in excessive power consumption, size and complexity.
A desirable system would be a unified solution to the symbol synchronization problem which does not require two distinct solutions, namely, a correlation based approach and a decision-directed approach.